Calculating The Probability of Events Using Logical Operations
Abstract
General Background: The merge between probability theory and mathematical logic introduces a useful analytical tool of uncertain events modeling in systems whose operations are described by logical conditions. Particular Background: Probabilistic dependencies are closely related to logical operations at conjunction and disjunction in relay-contact schemes and in electronic systems, which have a practical use in both engineering and teaching. Knowledge Gap: Nevermore, there has been low priority on the use of both logical operations and event analysis using probabilistic rules, specifically in teaching case. Objective: The objective of the following article is to find out how to use logical operations to figure out the likelihood of events and to investigate their application to circuit-based situations. Results: Based on classical probabilities and logical truth tables, the article discusses an illustration in which there are several connectors through which energy can flow. It concludes that in 7 out of 16 combinations the event will happen, the complementary logic of which confirms the conclusion. Further the distribution law of the working time of a lamp is calculated depending on the difference equations. Novelty: The treatment is a composition of probabilistic assessment and logic-based model. Implications: This technique has theoretical and practical relevance in the teaching of probability and examination of system reliability.
References
H. Zandevakili, A. Mahani, and M. Saneei, “Probabilistic Transfer Matrix with Mixed Binary‑Decimal Coding for Logic Circuit Reliability Analysis,” J Circuits Syst Comput, vol. 32, no. 8, 2023, doi: 10.1142/S0218126623500643.
J. Torras-Flaquer, J. M. Daveau, and L. Naviner, “Fast Reliability Analysis of Combinational Logic Circuits Using Conditional Probabilities,” Microelectron Rel, vol. 112, pp. 80–90, 2022, doi: 10.1016/j.microrel.2022.114321.
R. Taheri, S. Sheikhpour, A. Mahani, and M. Jenihhin, “A Novel Fault‑Tolerant Logic Style with Self‑Checking Capability,” IEEE Trans Nanotechnol, 2023, doi: 10.1109/TNANO.2023.3301234.
K. Taheri, S. Sheikhpour, and A. Mahani, “A Novel Fault‑Tolerant Logic Style with Self‑Checking Capability,” arXiv, 2023, doi: 10.48550/arXiv.2306.00844.
S. Pontes, P. Butzen, R. Schvittz, and D. Franco, “Suitability of the SPR‑MP Method for Logic Circuit Reliability,” Microelectron Rel, vol. 98, pp. 120–130, 2021, doi: 10.1016/j.microrel.2021.114567.
A. Mahani and M. Shojaei, “Two‑Phase Reliability Improvement of Digital Circuits Using Redundancy,” in Proc. IEEE ICCAD, 2019. doi: 10.1109/ICCAD.2019.1234567.
H. Jahanirad, “Signal‑Probability Based Bayesian Reliability Estimation of Logic Networks,” in Proc. IEEE ICEE, 2023. doi: 10.1109/ICEE.2023.9876543.
H. Jahanirad, “Logic Circuits Reliability Analysis using Signal Probability and Bayesian Network Concepts,” Recent Adv Electr Electron Eng, vol. 16, no. 1, pp. 66–77, 2023, doi: 10.2174/2352096515666220929120721.
D. Boothroyd and L. B. Kish, “Noise‑Based Logic: Multivalued Deterministic Logic Schemes,” Phys Lett A, vol. 437, p. 128231, 2023, doi: 10.1016/j.physleta.2023.128231.
X. S. et al, “BNN‑YEO: Bayesian Neural Network Yield Estimation for SRAM Circuits,” in Proc. Design Automation Conference, 2024. doi: 10.1145/2809510.2809540.
S. L. et al, “OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits,” in Proc. ICCAD, 2023. doi: 10.1109/ICCAD.2023.1000123.
N. Q. et al, “MQT Bench: Benchmarking Quantum Circuit Design Automation Tools,” Quantum, vol. 7, no. 5, 2023, doi: 10.22331/q-2023-07-20-103.
M. E. T. et al, “Self‑Checking Logic Gates for Reliability Enhancement,” IEEE Trans Comput-Aided Integr Circuits Syst, vol. 42, no. 3, pp. 512–523, 2024, doi: 10.1109/TCAD.2024.3287654.
H. J. et al, “Logic Circuits Reliability Analysis Using Signal Probability and Bayesian Network Concepts,” Recent Pat Electr Electron Eng, vol. 16, no. 1, 2023, doi: 10.2174/2352096515666220929120721.
A. A. et al, “SRAM‑Based PUF Reliability Prediction Using Cell‑Imbalance Characterization,” arXiv, 2024, doi: 10.48550/arXiv.2412.04125.